The landlord Published in: 10:59:41 2013-02-26
For. I need to do is to modify the driver, and to transplant the driver and application.
Recently in the debug FPGA extended serial port, the interrupt is always uncertain.
The principle is driven by the expansion of the FPGA 12 UART ports, respectively, using the IRQ0, IRQ3, IRQ4 three external interrupt. PowerPC writes the data to the buffer, and then FPGA gives it.
Break data through the extended serial port to send data out. Receiving data is the opposite direction. FPGA in the default is the low level, through the high level trigger interrupt.
The problem is the PowerPC manual, you can set the SEPCR register to achieve a high level of efficiency. But I load the driver and load the test program,
(1) IRQ is always low, and the PowerPC has low level triggered interrupt, and the interrupt is interrupted.
(2) even when the FPGA is extended to the IER interrupt enable register to write data, directly led to the crash.
(3) when I was in the interrupt processing, in the IRQ_HANDLED returne before, write 1 to remove the interrupt, bugverbose debug info kernel.
Have been engaged for several days, always make a. Ask you what this is how?
I am now in doubt: 1, PowerPC in the initialization, set the interrupt mask register, remove the interrupt suspend register, polarity active (high), trigger mode
Memory device (edge trigger or level trigger). Is that enough?
2, IRQ PowerPC above the line, the manual is said to support the high level trigger, do not support the high level trigger it?
3, if you do not support the high level trigger, the FPGA add a reverse device, to achieve a low level trigger can it?
Test character superimposed, with out_8 (), in_8 () to send an acceptable function, has been able to achieve. Problems should focus on the PowerPC interrupt.
We have any ideas, please enlighten ah. In addition, you can also introduce learning PowerPC good information, good site ah. Thank you all first.
#1 Score: 0 Reply to: 21:19:53 2014-03-08
Is there an operating system?